library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;
    
entity SEXT is
    port(IR_out: in unsigned(15 downto 0);
         PCoffset11: out unsigned(15 downto 0);
         PCoffset9: out unsigned(15 downto 0);
         PCoffset8: out unsigned(15 downto 0);
         Imm7: out unsigned(15 downto 0));
    end entity SEXT;
     
architecture build of SEXT is
    begin
        process(IR_out)
            begin
                if IR_out(10) = '1' then
                    PCoffset11 <= "11111" & IR_out(10 downto 0);
                else
                    PCoffset11 <= "00000" & IR_out(10 downto 0);
                end if;
                ---
                if IR_out(8) = '1' then
                    PCoffset9 <= "1111111" & IR_out(8 downto 0);
                else
                    PCoffset9 <= "0000000" & IR_out(8 downto 0);
                end if;
                ---
                if IR_out(7) = '1' then
                    PCoffset8 <= "11111111" & IR_out(7 downto 0);
                else
                    PCoffset8 <= "00000000" & IR_out(7 downto 0);
                end if;
                ---
                if IR_out(6) = '1' then
                    Imm7 <= "111111111" & IR_out(6 downto 0);
                else
                    Imm7 <= "000000000" & IR_out(6 downto 0);
                end if;
            end process;
    end build;
